The present invention relates generally to synthesis of digital circuitry and, more specifically, to systems and methods for obtaining timing closure in digital circuitry design.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Certain electrical devices, such as programmable logic devices (PLDs) and application specific integrated circuits (ASICs), may have circuitry elements that may exchange data via a bus or a wire that may have large latencies. For example, certain field-programmable gate arrays (FPGAs) may have programmable fabric region (e.g., core) that may be customized by a user, and a hardened circuitry region (e.g., hardened logic region, fixed circuitry, periphery) that may provide interface functionality to the FPGA that may be used by the custom logic. The synchronous logic in the programmable fabric region may be clocked by a clock tree, which may be generated during the FPGA synthesis process by the user. As such, the latency of the clock provided to the programmable fabric region may vary based on the FPGA design. The hardened logic, by contrast, may have a fixed clock latency that may be determined by during the synthesis of the hardened logic circuitry and may be different from the clock latency of the programmable fabric region. The differences in the clock latency in the programmable fabric region and the hardened region may lead to clock skews, which may affect performance and/or failure of the circuit. While certain synthesis process in computer assisted design (CAD) tools may reduce these clock skews, the variable latency of programmable fabric region may lead to unavoidably large clock skews, which may interfere significantly in the transfer of data between registers in the programmable fabric region and registers in the hardened logic region.